Critères de l'offre
Métiers :
- Digital engineer
Expérience min :
- 3 à 20 ans
Secteur :
- Food industry
Compétences :
- English
- French
- Verilog
- IP
- CPU
- + 3 compétences
Lieux :
- Neuchâtel
Conditions :
- Permanent contract
- Full Time
L'entreprise : Michael Page
Join our client's cutting-edge team in their R&D Hub in Neuchatel, where they develop miniature, highly reliable, low-power devices that power critical health and connectivity solutions like hearing aids and glucose monitors.
Description du poste
As the Digital IC Design Engineer (Staff or Principal), you will play a pivotal role in shaping product lines, driving innovation, and ensuring technical excellence. In this senior-level role, your mentotship and technical expertise will guide project success, from initial architecture through to final implementation.
Key Responsibilities:
- Mentor a team of engineers, fostering a collaborative and innovative environment.
- Architect, specify, implement, simulate, and benchmark MCU, DSP systems, and hardware accelerators that push the boundaries of technology.
- Spearhead improvements in design methodology and workflows, ensuring the team stays at the cutting edge of semiconductor development.
- Collaborate with product integration teams to define, integrate, and optimize these systems.
- Lead the verification process and FPGA prototyping of systems to ensure robust and reliable designs.
- Coordinate closely with the software team to guide SDK development for these systems, enabling seamless software-hardware integration.
Description du profil
We are looking for an innovative and experienced IC Digital Design Engineer with a passion for cutting-edge technologies and a track record of delivering high-impact semiconductor designs.
General skills :
- Degree in Electrical Engineering or a related technical field.
- 5 to 8+ years of experience in semiconductor product development,
- Expertise in embedded CPUs and AMBA bus protocols (AHB/APB).
- Experience in RTL design of digital IP blocks and systems, using Verilog/SystemVerilog.
- Deep knowledge of design intent methodologies, including timing constraints (SDC) and power intent (UPF).
- Write Technical documentation and communicate complex ideas clearly.
- Fluent English is required; French is a plus.
Bonus Skills:
- Experience with CPU/MCU design, SystemRDL, or IP-XACT.
- RISC-V architecture,
- Experience in Python and C/C++
- RTL-to-GDS flow, including logic synthesis, place-and-route, STA, and power analysis.
- Digital verification methodologies, such as UVM.